The present invention relates to algorithmic pattern generators in automatic test equipment for testing circuits, and more particularly to algorithmic pattern generators useful for testing semiconductor random access memory arrays embedded in logic and semiconductor random access memory devices, and more particularly for testing synchronous DRAM devices.
Automatic pattern generators (APGs) are well-known components of automatic test equipment (ATE) for electronic circuits. APGs exist to create patterns of test vectors on-the-fly for testing integrated circuits. The testing of memory arrays (embedded in logic or microprocessor devices, for example) and memory devices (such as synchronous dynamic random access memory devices) is an important application of APGs. New memory devices are faster and larger than previous generation devices. They also pose new challenges to the algorithmic generation of test vectors--multi-cycle latency, pipelining, non-linear address sequencing, and synchronous operation.